I. Field
The present disclosure generally relates to systems and methods of reducing power consumption in memory, and more particularly to systems and methods for limiting power consumption of wordlines in a memory bank.
II. Description of Related Art
Advances in technology have resulted in smaller and more powerful personal computing devices. For example, a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular (analog and digital) telephones and internet protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can include a web interface that can be used to access the Internet. As such, these wireless telephones include significant computing capabilities.
Typically, portable computing devices are battery-powered. Consequently, the electronic circuits for the portable devices are often required to meet stringent energy requirements. Since the number of transistors on a chip continue to increase while the threshold voltages of these transistors continues to decrease, leakage energy via the transistors is becoming increasingly important.
Current microprocessors generally include dense cache memories that include numerous transistors. It has been estimated that leakage energy accounts for 30 percent of level 1 (L1) cache energy consumed by a 65 nm part in active operation mode and 80 percent of level 2 (L2) cache energy for a semiconductor device manufactured using a 0.13 micron process.
As the gap between processing frequencies and Dynamic Random Access Memory (DRAM) access times has continued to widen, semiconductor device manufacturers have increasingly utilized on-die Static Random Access Memory (SRAM) to meet performance requirements. Consequently, in many chips, the SRAM arrays may occupy as much as 60 percent of the die area. Since most of the SRAM circuit elements are idle at any given time, the SRAM arrays are significant sources of current leakage.
It has been proposed to gate the power supply to wordline logic along a memory addressable unit when the processor is in a special power-save mode, such as a sleep mode (where the SRAM state is restored on wakeup) or a stop mode (where the SRAM contents are invalidated). These modes are typically controlled by software and add to device complexity and overhead.
Accordingly, it would be advantageous to provide an improved power control mechanism for reducing current leakage for memory devices.